Implant-controlled-channel vertical JFET

ABSTRACT

We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor devices and particularly to animproved junction field effect transistor (JFET).

A conventional JFET is a three-terminal semiconductor device in which acurrent flowing substantially parallel to the top surface of thesemiconductor chip is controlled by an externally applied verticalelectric field, as shown in FIGS. 1 a, 1 b, and 1 c. It can be used as aswitch or an amplifier. JFET is known as the unipolar transistor becausethe current is transported by carriers of one polarity, namely, themajority carriers. This is in contrast with the bipolar junctiontransistor, in which both majority-and-minority-carrier currents areimportant.

A typical n-channel JFET fabricated by the standard planar process isshown in FIG. 1. FIG. 1 a depicts a JFET built in a semiconductorsubstrate in an epitaxial layer. FIG. 1 b depicts a JFET fabricated by adouble-diffused technique in a bulk semiconductor substrate. FIG. 1 c isa schematic representation of both JFETs.

The active region of the JFET consists of a lightly doped n-type channelsandwiched between two heavily doped p⁺-gate regions. In FIG. 1 a, thelower p⁺ region is the substrate, and the upper p⁺ region is formed byboron diffusion into the epitaxially grown n-type channel. The p⁺regions are connected either internally or externally to form the gateterminal. Ohmic contacts attached to the two ends of the channel areknown as the drain and source terminals through which the channelcurrent flows. Alternatively, the JFET may be fabricated by thedouble-diffused technique with a diffused channel and an upper gate asillustrated in FIG. 1 b. In both cases, the channel and the gate regionsrun substantially parallel the top surface of the substrate, so does thecurrent flow in the channel.

When a JFET operates as a switch, without a gate bias voltage, thetransistor has a conducting channel between the source and the drainterminals. This is the ON state. To reach the OFF state, areverse-biasing gate voltage is applied to deplete all carriers in thechannel.

The reverse voltage bias applied across the gate/channel junctionsdepletes free carriers from the channel and produces space-chargeregions extending into the channel. With a gate voltage set between ONand OFF levels, the cross-sectional area of the channel and the channelresistance can be varied. Thus the current flow between the source andthe drain is modulated by the gate voltage.

An important figure of merit of a JFET is its cutoff frequency (f_(co)),which can be represented mathematically as follows:f _(co) ≦q a ²μ_(n) N _(d)/(4πkε _(o) L ²),where q is the electric charge of the charge carriers, a is the channelwidth, μ_(n) is the mobility of the charge carriers, N_(d) is the dopingconcentration in the channel, k and ε_(o) are the dielectric constantand the electrical permittivity of the semiconductor material and thefree space respectively, and L is the channel length.

Another important figure of merit of a JFET is the noise figure. Atlower frequencies the dominant noise source in a transistor is due tothe interaction of the current flow and the surface region that givesrise to the 1/f noise spectrum.

This invention provides a JFET device that has superior f_(co) and 1/fperformance over conventional JFETs and a process of making the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is a partial sectional depiction of a semiconductor substratewith a JFET device built in it.

FIG. 1 b is a partial sectional depiction of a semiconductor substratewith another JFET device built in it.

FIG. 1 c is a schematical representation of a JFET.

FIG. 2 is a partial sectional depiction of a semiconductor substratewith a JFET embodying the invention built in it.

FIG. 3 is a cross-sectional depiction of a partially completed JFET 10embodying this invention.

FIG. 4 is a cross-sectional depiction of a further partially completedJFET 10 embodying this invention.

FIG. 5 is a cross-sectional depiction of a further partially completedJFET 10 embodying this invention.

FIG. 6 is a cross-sectional depiction of a further partially completedJFET 10 embodying this invention.

FIG. 7 is a cross-sectional depiction of a further partially completedJFET 10 embodying this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 2, an n-channel JFET 10 is shown as a three-terminal device,fabricated near the surface of a semiconductor substrate surface. Thesemiconductor material in the preferred embodiment is silicon. A JFETembodying this invention can also be fabricated in other semiconductormaterials such as germanium, germanium-silicon, gallium arsenide orother compound material. FIG. 2 depicts a JFET built in a bulk siliconsubstrate. A JFET embodying this invention can also be fabricated in asubstrate of semiconductor-on-insulator such as SIMOX,silicon-on-sapphire, or in bonded wafer. FIG. 2 depicts an n-channelJFET. A JFET embodying this invention can also be implemented as ap-channel JFET. A JFET may also be one device in an integrated circuitthat includes CMOS and Bipolar circuit elements, and passive circuitcomponents.

The substrate 110 may be either n-type or p-type. In a typicalintegrated circuit fabricated by a BiCMOS process, the substrate 110would be a lightly doped, p-type crystalline silicon material. Over aportion of the substrate 110 is an n-type layer 150 of low resistivitythat constitutes the drain portion of the JFET. In a BiCMOS structure, aregion commonly referred to as “a buried layer” fits this requirement.

Over a portion of the buried layer 150 is layer 200. Layer 200 includesseveral regions of different materials. Among them, region 220 includesprimarily dielectric material. In this embodiment, this material issilicon dioxide, fabricated with a STI technique. Region 220 may also bebuilt with a LOCOS technique or other techniques well known in the art.Element 210 of layer 200 is substantially p-type mono-crystallinesilicon. It may be formed by an epitaxial technique.

Elements 320 are gate regions of the JFET, located above layer 200. Theyare polycrystalline silicon, heavily doped with p-type dopant. A portionof the p-type dopant diffuses into the adjacent lightly doped p-region310, which is mono-crystalline. The combination of elements 310 and 210makes up a mono-crystalline region that contains the channel region 350of the JFET.

The channel may be created by implanting n-type ions perpendicular tothe substrate surface. The dopant concentration in the channel region isusually not uniform. In fact, it is advantageous to be able to tailorthe doping profile, for example, so that the dopant concentration in thechannel region near the surface of the substrate is lower than thedopant concentration distant from the surface of the substrate. Thisdopant profile places the pinch-off region closer to the top of layer310 and uses the shallow portion of the implanted ions to set thepinch-off voltage of the JFET. Such a profile may be accomplished with amultiple-implant process. The multiple implants may be of variousdosages and implant energies. In this embodiment, we employ athree-implant process—one at 220 keV, one at 340 keV and one at 500 keV.

The source region 450 in this embodiment is poly-crystalline. It makescontact to the channel region 350 through an opening 415 etched outthrough an insulating element that comprises a silicon dioxide element410 and a silicon nitride element 420. In the preferred embodiment,there is an absence of native oxide between the source region 450 andthe channel region 350 so the source region contacts the channel regionand the silicon immediately above the channel region may retain themono-crystalline structure within a short range. In another embodiment,minute oxide may exist in the vicinity of the opening 450 as result ofchemical processes such as a wet chemical cleanup process. The sourceregion 450 is heavily doped with phosphorus, arsenic, or other n-typedopants and it partially overhangs the gate regions 320 and is insulatedfrom the gate region 320 by silicon dioxide elements 410, siliconnitride elements 420, oxide elements 460 and nitride elements 470.

FIGS. 3 to 7 depict the channel portion of a JFET embodying thisinvention through a fabrication process. The complete fabrication of afunctional JFET, in the context of an integrated circuit, involves manywell-known processes in addition to those illustrated in the drawings.These well-known processes include creating a drain contact to theburied layer, a source contact to the source region, and a gate contactto the gate region, and wiring the contacts with metallic elements toconnect the JFET to the other circuit elements of the integratedcircuit.

FIG. 3 depicts a cross-sectional view of a partially completed JFET 10embodying this invention. Element 110 is a semiconductor substrate. Inthis embodiment, the semiconductor material is silicon. Othersemiconductor materials suitable to implement this invention includegermanium, silicon-germanium, silicon carbide, and gallium arsenide. Inthis embodiment, the silicon substrate is a bulk substrate. Other typeof substrate suitable to implement this invention includes silicon oninsulator (SOI).

Substrate 110 may be doped with a p-type or n-type dopants. The dopantconcentration may vary from light to heavy as understood by a personwith reasonable skill in the art of semiconductor processing.

Element 150 is a heavily doped semiconductor layer partially coveringthe substrate 110. In this embodiment, layer 150 is formed by an arsenicor phosphorus implant step followed by a anneal step. In the art ofsemiconductor processing, this heavily doped region is referred to as “aburied layer”.

Layer 200 sits on top of the buried layer. In this embodiment, layer 200is an epitaxial, lightly doped, p-type mono-crystalline-silicon layer.The thickness of this epi-layer may be between 2000 Å and 7000 Å,preferably about 5000 Å. Layer 200 may be doped in-situ. It may also bedoped with a boron implant with a dose between 5×10⁹ to 5×10¹¹ ions/cm²,to a dopant concentration of about 1×10¹⁵ ions/cm³.

Layer 200 also includes regions of dielectric material to insulate theJFET electrically from the adjacent circuit elements. The dielectricregions 220 are places in the layer 200 such that the JFET is formed ina mono-crystalline silicon island 210. In this embodiment, thedielectric material is silicon dioxide and the technique with which thesilicon dioxide regions are formed is referred to in the art as theshallow trench isolation (STI) technique.

FIG. 4 depicts a cross-sectional view of a further partially completedJFET 10. Features depicted in FIG. 4 include a layer element 300. Inthis embodiment, layer 300 is another lightly doped, p-type,silicon-epi-layer. The thickness of layer 300 may be between 1000 Å and3000 Å, preferably 2000 Å. Layer 300 may be doped in-situ or it maybedoped with a boron implant with dose between 5×10⁹ and 5×10¹¹ ions/cm²,preferably to a dopant concentration of about 1×10¹⁵ ions/cm³.

The portion of epi-layer 300 that is in contact with element 210 ismono-crystalline while the portion that contacts element 220 ispoly-crystalline.

FIG. 5 depicts a cross-sectional view of yet a further partiallycompleted JFET 10 embodying this invention. Features depicted in FIG. 5include a region 350 enclosed in the region 210, and a layer 400 thatcomprises a patterned photoresist layer 430, a silicon nitride layer420, and a silicon dioxide layer 410. The nitride and oxide layers aredepicted in FIG. 5 as after a portion, uncovered by the photoresistpattern 430, has been removed by an etching technique well known in theart of semiconductor processing. The etched portion includes a region415. Instead of a silicon-nitride, silicon oxide layer combination inlayer 400, the JFET may also be fabricated by using a single oxidelayer, or nitride layer, or oxynitride layer.

The region 350 is the n-channel region of the JFET, it maybe formed byimplanting n-type ions into region 210 through the opening 415. In thisembodiment, the channel is formed with a three-step ion-implant process.One implant is at 200 keV, another implant is at 340 keV, and anotherimplant is at 500 keV. Dosages of phosphorus ions that may range from2×10⁹ to 4×10¹¹ ions/cm² per implant are used in the 3-step implant—withthe higher energy implants typically associate with higher doses. Othern-type ion species and implant dosages and energies may also be used totailor the channel doping profile to suit specific circuit requirement.

FIG. 6 depicts a cross-sectional view of yet a further partiallycompleted JFET 10 embodying this invention. Features depicted in FIG. 6include a layer element 500. In this embodiment, the layer 500 ispolysilicon, with a thickness between 1 kÅ and 3 kÅ. At the vicinity ofopening 415, where layer 500 contacts channel 350, the crystal mayfollow the structure of the channel region and remains mono-crystalline.

FIG. 6 also depicts a photoresist pattern 510. This pattern defines thesource electrode area and the gate electrode area, as will be furtherillustrated in FIG. 7.

FIG. 7 depicts a cross-sectional view of yet a further partiallycompleted JFET 10 embodying this invention. Features depicted in FIG. 7include a source element 450, a gate element 320, and sidewall elements460 and 470.

In this embodiment, the source element 450 and the gate element 320 areformed with a poly etch process well known in the art of semiconductorprocessing. The etching action removes the portion of layer 500 that isnot protected by the photoresist pattern 510 and the portion of layer300 that is not protected by oxide element 410 and nitride element 420.Element 470 and element 460 are referred in the art of semiconductorprocessing as the sidewalls. They are formed by a technique combining afilm deposition and a film etching. The etching action not only removesthe newly deposited film but also a portion of the oxide element 410 andnitride element 420 that is not covered by the source element 450 or thesidewall elements 460 and 460. At the completion of the etching process,the silicon surfaces of the source element 450 and the gate element 320are uncovered.

FIG. 7 also depicts the source and gate implant processes. In thisembodiment, the gate-implant species is boron, the dose is 3×10¹⁵ions/cm², and the implant energy is 20 keV. The source implant speciesis arsenic, the dose is 1.5×10¹⁵ ions/cm², and the implant energy is 50keV. Other implant species, dosages and energies maybe used to effectlow resistivity in the source and gate-poly-regions.

Contrary to conventional JFETs, as depicted in FIGS. 1 a, 1 b, and 1 c,which have their channel substantially parallel and proximate to the topsurface of the semiconductor substrate, the JFET embodying thisinvention has a “vertical” channel.

It is well known in the art of semiconductor physics that the topsurface of the semiconductor substrate is heavily populated withimperfections such as charge traps and surface states. The interactionbetween the charge carrier in the channel and the surface imperfectionsis partially responsible for the performance limitation of conventionalsemiconductor devices in which the current flows parallel to and nearthe surface.

In contrast, the “vertical” channel in the present invention channelsthe flow of the charge carriers in a direction substantiallyperpendicular to the “surface” of the semiconductor surface. Thus theinteraction between the charge carrier and the surface imperfection issubstantially reduced, which enables the JFETs embodying this inventionto have superior cutoff frequency (f_(co)) and 1/f noise figure.

1-23. (canceled)
 24. An method for making an electronic device,comprising a. providing a semiconductor substrate of a firstconductivity, having a top surface and a bottom surface; b. forming aburied layer of a second conductivity near the top surface; c. forming afirst semiconductor-layer over the buried layer, doping the region withdopant of the first conductivity; d. forming in the first layerinsulation regions that isolate an island of the first-layer material,the insulation regions having substantially the same thickness as thefirst layer so the insulation regions reaches the buried layer; e.forming a second semiconductor-layer of the first conductivity over thefirst semiconductor-layer and the insulation regions, portions of thesecond layer over the insulation regions being polycrystalline, portionsof the second layer over the first layer being mono-crystalline; f.forming a dielectric layer over the second layer; g. implanting dopantof the second conductivity into the island of the first semiconductorlayer to form a channel-region in the first and the secondsemiconductor-layer that reaches the buried layer; h. forming a thirdsemiconductor-layer of the second conductivity over the dielectriclayer; i. patterning and etching the third semiconductor-layer and thedielectric layer to form a gate structure and uncovering a portion ofthe second semiconductor-layer; and j. implanting dopant of the firstconductivity into the uncovered second semiconductor-regions to form agate structure.
 25. The method in claim 24, in which the semiconductorsubstrate is silicon.
 26. The method in claim 24, in which theinsulation regions comprise silicon dioxide formed with a STI technique.27. The method in claim 24, in which the first semiconductor layer isabout 0.5 micrometers thick and the second semiconductor layer is about0.2 micrometers thick.
 28. The method in claim 24, in which thedielectric layer comprises silicon dioxide and silicon nitride.
 29. Themethod in claim 24, in which the implanting into the first semiconductorlayer comprises three implant energies and three implant dosages. 30.The method in claim 24, in which a portion of the dopant implanted intothe gate structure diffuses into the mono-crystalline portion of thesecond semiconductor layer.
 31. The method in claim 24, in which thefirst conductivity is p-type.
 32. The method in claim 24, in which thefirst conductivity is n-type.
 33. A method for making an n-channelsilicon JFET, comprising a. providing a p-type silicon substrate, havinga top surface and a bottom surface; b. forming a buried layer ofmono-crystalline silicon near the top surface, doped with a n-typedopant to a sheet resistance of about 25 ohms per square; c. forming a0.5 micrometers silicon mono-crystalline first layer over the buriedlayer, doping the region with p-type dopant to a concentration of about1×10¹⁵ dopant ions per cubic centimeter; d. forming in the first layerinsulation regions that isolate islands of the first-layer material, theinsulation regions having substantially the same thickness as the firstlayer so the insulation regions contact the buried layer; e. forming a0.2 micrometer silicon second layer over the first layer and theinsulation regions, portions of the second layer over the insulationregions being polycrystalline silicon, portions of the second layer overthe first layer being mono-crystalline silicon, doping the second layerwith p-type dopant to a concentration of about 1×10¹⁵ dopant ions percubic centimeter; f. forming a dielectric layer of silicon dioxide andsilicon nitride over the second layer; g. patterning and etching thedielectric layer to form a opening region free of the dielectricmaterial over the second layer; h. implanting n-type dopant through theopening region to form a n-type channel-region that reaches the buriedlayer; i. forming a third n-type silicon layer over the dielectriclayer; j. patterning and etching the third silicon layer and thedielectric layer to form a source structure and uncovering a portion ofthe second silicon layer; and k. implanting p-type dopant into theuncovered second-silicon regions to form a gate structure.